ParBert 81250

A. 주요사양

– 멀티 포트 기가비트 디바이스의 정확한 특성분석을 위한 모듈러 BERT 플랫폼

Selection Guide for ParBERT 81250

target Data rate range

333.334 kb/s to 675 Mb/s

20.834 Mb/s to 3.35 Gb/s

620 Mb/s to 7 Gb/s

620 Mb/s to 13.5 Gb/s

Data module back-ends

E4832A

E4861A

N/A

N/A

Generator front ends

E4838A

E4862A

N/A

N/A

Analyzer front ends

E4835A

E4863A

N/A

N/A

Generator modules

N/A

N/A

N4874A

N4872A

Analyzer modules

N/A

N/A

N4875A

N4873A

Compatible clock modules

E4805B/E4808A/E4809A

E4808A/E4809A

E4809A

E4809A

Max. number of channels, 1 Frame / 3 frames

44 / 132

22 / 66

10 / 30

10 / 30

Adressed I/O technology

LVDS, PECL, ECL, TTL, 3.3V CMOS

LVDS, CML, PECL, ECL, low voltage CMOS

LVDS, CML, PECL, ECL, low voltage CMOS

LVDS, CML, PECL, ECL, low voltage CMOS

Data capability

PRWS/PRBS

PRWS/PRBS

PRWS/PRBS

PRWS/PRBS

User memory

2 Mb

16 Mb

64 Mb

64 Mb

Input / Output

differential &single ended

differential &single ended

differential &single ended

differential &single ended

Data format

RZ, R1, NRZ, DNRZ

RZ, R1, NRZ, DNRZ

NRZ, DNRZ

NRZ, DNRZ

Transition times 20%-80%

0.5-4.5ns, var (10-90%)

<75ps

<20ps

<20ps

Amplitude resolution

0.1-3.5V, 10mV

0.05V-1.8V, 10mV

0.1 1.8V, 5mV

0.1 1.8V, 5mV

Window

-2.2 to 4V

-2 to 3.5V

-2 to 3V

-2 to 3V

Input voltage ranges

0 to 5V -2 to 3V

-2 to 1V, -1 to 2V, 0 to 3V

-2 to 3V, 2Vpp

-2 to 3V, 2Vpp

Sensitivity

50mV typ., diff.

<50mV

<50mV

<50mV

Sample delay resolution

2ps

1ps

100fs

100fs

C. 제품 관련 자료

(제품개요) Par BERT 81250 Parallel Bit Error Ratio Tester 다운